A Novel Approach to PCI Simulation Using ScriptSim
description- – In recent years, the Peripheral Component Interconnect (PCI) has become one of the most widely used bus architectures in modern computers. Simulation of the PCI bus, however, has been limited in both research and development. Current commercial PCI simulation software is designed towards compliance and verification testing rather than accurately mimicking PCI bus systems. In addition, most PCI simulation software is inflexible and offers no graphical user interface, instead relying on text files for configuration.This paper presents a novel approach to PCI simulation using ScriptSim, an open-source PCI simulation tool that supports all the features offered by the PCI Local Specification Version 2.2. In addition to extending ScriptSim to include PCI-X functionality and a web-based graphical interface, we introduce techniques that allow us to accurately simulate real-world systems.
- – 2008-01-01
- – application/pdf
Design of a Two-Receiver Interferometer on Motorized Tracks
description- – A 94.8 GHz interferometric imaging system utilizing aperture synthesis and tomography is developed for the Center for Advanced Sensor and Communication Antennas. Whereas typical interferometer designs employ multiple antennas to synthesize an aperture for image reconstruction, this unique interferometer will reproduce a scene's brightness temperature with only two antennas. To achieve this, the aperture synthesis is done with one antenna remaining stationary while the second antenna is moved at discrete increments along two controlled tracks. The two signals received by the antennas are cross-correlated to produce measured visibility function samples. The visibility samples reconstruct the scene brightness temperature through an inverse Fourier transform relationship.
- – 2008-01-01
- – application/pdf
Miniaturization of Microstrip Patch Antennas for GPS Applications
description- – The desire to incorporate multiple frequency bands of operation into personal communication devices has led to much research on reducing the size of antennas while maintaining adequate performance. GPS is one such application, where dual frequency operation, bandwidth and circular polarization pose major challenges when using traditional miniaturization techniques. Various loading methods have been studied to reduce the resonant frequency of the antenna - high permittivity dielectric loading, slot loading and cavity loading - while examining their effects on bandwidth and gain. The objective of this thesis is to provide guidelines on what is achievable using these miniaturization methods and insight into how to implement them effectively.
- – 2008-01-01
- – application/pdf
An Orthogonally-Fed, Active Linear Phased Array of Tapered Slot Antennas
description- – An active, broadband antenna module amenable for use in low cost phased arrays is proposed. The module consists of a Vivaldi antenna integrated with a frequency conversion integrated circuit. A method of orthogonally mounting endfire antennas onto an array motherboard is developed using castellated vias. A castellated active isolated Vivaldi antenna package is designed, fabricated, and measured. An 8x1 phased array of castellated, active Vivaldi antenna packages is designed and assembled. Each element has approximately one octave of bandwidth centered in X-band, and each is mounted onto a coplanar waveguide motherboard. Radiation patterns of the array are measured at several frequencies and scan angles.
- – 2008-01-01
- – application/pdf
METALLIC CARBON NANOTUBES, MICROWAVE CHARACTERIZATION AND DEVELOPMENT OF A TERAHERTZ DETECTOR
description- – It is reported that terahertz radiation from 0.69 to 2.54 THz has been sensitively detected in a device consisting of bundles of carbon nanotubes containing single wall metallic carbon nanotubes,quasi-optically coupled through a lithographically fabricated antenna, and a silicon lens. The measured data are consistent with a bolometric detection process in the metallic tubes and thedevices show promise for operation well above 4.2 K. Microwave measurements have also been done up to 20GHz. Voltage responsivity got here is comparable to that of the Schottky diode detector. The detection at microwave frequencies are consistent with the diode detection mode. S11 parameters of different devices were measured using microwave probing, and de-embedding process has been done to get the impedances of the SWNTs. A circuit model was fitted based on the measurement data, and different values of the elements of the circuit are extracted. Frequency response from the circuit model is consistent with the experimental data.
- – 2008-01-01
- – Fu, Kan
- – application/pdf
MIMO Communication for Ad Hoc Networks: A Cross Layer Approach
description- – New technologies such as pervasive computing, ambient environment, and communication avid applications such as multimedia streaming are expected to impact the way people live and communicate in the wireless networks of the future. The introduction of these new technologies and applications is, however, a challenging task in wireless networks because of their high bandwidth requirements and Quality of Service (QoS) demands.A significant recent advance in wireless communication technology, known as Multiple-Input Multiple-Output (MIMO) provides unprecedented increase in link capacity, link reliability and network capacity. The main features of MIMO communication are spatial multiplexing, point-to-multipoint and multipoint-to-point transmission as well as interference suppression in contrast to the conventional single antenna (Single-In Single-Output, SISO) networks.In this thesis, we investigate the problem of scheduling flows for fair stream allocation (or, stream scheduling) in ad hoc networks utilizing MIMO antenna technology. Our main contributions include: i) the concept of stream allocation to flowsbased on their traffic demands or class, ii) stream allocation to flows in the network utilizing single user or multiuser MIMO communication, iii) achieving the proportional fairness of the stream allocation in the minimum possible schedule length, and iv)performance comparison of the stream scheduling in the network for single user and multiuser communication and the tradeoff involved therein. We first formulate demand based fair stream allocation as an integer linear programming (ILP) problem whose solution is a schedule that is guaranteed to be contention-free. We then solve this ILP in conjunction with binary search to find a minimum length contention-free schedule that achieves the fairness goals. Performance comparison results show the benefit of multiuser MIMO links over single user links which is predominant at higher traffic workloads in the network. We also implement a greedy heuristic for stream scheduling and compare its performance with the ILP-based algorithm in terms of the fairnessgoals achieved in a given schedule length. OPNET-based stochastic simulation confirms the benefits of MIMO-based stream scheduling over single antenna links, as shown by our theoretical analysis.
- – 2008-01-01
- – application/pdf
Supply Current Modeling and Analysis of Deep Sub-Micron CMOS Circuits
description- – Continued technology scaling has introduced many new challenges in VLSI design. Instantaneous switching of the gates yields high current flow through them that causes large voltage drop at the supply lines. Such high instantaneous currents and voltage drop cause reliability and performance degradation. Reliability is an issue as high magnitude of current can cause electromigration, whereas, voltage drop can slow down the circuit performance. Therefore, designing power supply lines emphasizes the need of computing maximum current through them. However, the development of digital integrated circuits in short design cycle requires accurate and fast timing and power simulation. Unfortunately, simulators that employ device modeling methods, such as HSPICE are prohibitively slow for large designs. Therefore, methods which can produce good maximum current estimates in short times are critical. In this work a compact model has been developed for maximum current estimation that speeds up the computation by orders of magnitude over the commercial tools.
- – 2007-01-01
- – application/pdf
Global Interconnects in the Presence of Uncertainty
description- – Global interconnect reliability is becoming a bigger issue as we scale down further into the submicron regime. As transistor dimensions get smaller, variations in the manufacturing process, and temperature variations may cause undesired behavior, and as a result, compromise performance. This work makes an effort to characterize the effects of such variations, to provide designers with a guideline for making designs tolerant to these variations while benefiting from tighter design margins.Since interconnects contribute to most of the delay and power on a chip, interconnect performance becomes a primary issue in design. One of the main concerns when considering physical transistor dimension variations is the effect on delay. Due to smaller transistor dimensions, the photolithographic process may produce transistors with significant variations from the ideal physical dimensions. Such variations cause delay uncertainty which can lead to over or underestimation in the design phase. This work examines interconnects to establish a guideline of the effect that process variations have on delay. A repeated interconnect is analyzed and the effects of physical device variations on delay are observed. Given the delay distribution in the presence of Leff variation, a supply voltage assignment technique is proposed to correct the observed deviation from the nominal delay on a long, repeated interconnect. This technique results in a significant reduction of the delay distribution, with a negligible power overhead.After looking at static variation effects on interconnect performance, this thesis addresses thermal variations on global signals, which cause delay degradation and may lead to timing failures. Given the presence of a large thermal gradient along a clock signal in a data path clocked by two leaves of an H-tree, several thermal scenarios which can compromise timing are discussed. A buffer-based skew compensation technique is proposed to correct the effect of thermal and manufacturing variations on this system.Having characterized repeated interconnect performance under process variations, the bandwidth of the line can be more effectively utilized by using a technique called phase coding. Phase coded interconnects are introduced in the context of using them once an interconnect has been adequately modeled in the presence of variations.With guidelines quantifying the effects of process variations on interconnect techniques and careful characterization, designers can factor these considerations into their design process, reducing the variation from the nominal expected behavior and allowing for smaller design margins. This will lead to more reliable products as we advance into future technologies and transistor dimensions get smaller.
- – 2007-01-01
- – application/pdf
A KA BAND SWITCH-LNA MMIC FOR RADIOMETRY APPLICATIONS
description- – The need for low cost and low size radiometers have encouraged many to look at the implementation of radiometers using MMICs. Compared to their waveguide counterparts, radiometers implemented with MMICs significantly reduce the size and weight of the radiometer, while still maintaining satisfactory electrical performance at millimeter wave frequencies. Utilizing MMICs can also help in significantly lowering the noise temperature of the radiometer, specifically, metamorphic high electron-mobility transistors (mHEMT) have demonstrated very low noise, high gain performance and comparably low cost. This thesis is focused on designing a combined switch and low noise amplifier IC at 36.5 GHz that lowers the radiometer noise temperature while allowing for an accurate calibration. The measured gain from straight and 90 degree input of the switch-LNA, at 36.5 GHz, was 6.6 dB and 7.1 dB, respectively. Likewise, the noise figure of the MMIC was 3.8 dB and 3.3 dB, respectively. The mHEMT implemented SPDT switch has a measured insertion loss, at 36.5 GHz, of 1.3 dB and 0.88 dB with isolation of 25 dB and 36 dB, respectively. The calculated temperature sensitivity based on measured temperature variations was 0.273 K at 36 GHz.
- – 2007-01-01
- – application/pdf
Automatic Techniques for Modeling Impact of Sub-wavelength Lithography on Transistors and Interconnects and Strategies for Testing Lithography Induced Defects
description- – For the past four decades, Moore's law has been the most important benchmark in microelectronic circuits. Continuous improvement in lithographic technology has key enabler for growth in transistor density. In recent times, the wavelength of the light source has not kept its pace in scaling. Consequently, modern devices have feature sizes that are smaller than the wavelength of light source used currently in lithography. Printability in sub-wavelength lithography is one of the contemporary research issues. Some of the printability issues arise from optical defocus, lens aberration, wafer tilting, isotropic etching and resist thickness variation. Many of such sources lead to line width variation in today's layouts. In this work we propose to simulate such lithographic variation and estimate their impact on current devices and interconnects. We also propose to model such effects and aim to provide measures at the design level to mitigate these problems. Variations arising out of lithography process also impact yield and performance. We plan to study the impact of sub-wavelength lithography on yield and provide solutions for its measure, and directed pattern developement and testing.
- – 2007-01-01
- – application/pdf
Operation And Improvement Of The IWRAP Airborne Doppler Radar/Scatterometer
subjectcollectiondate- – 2007-01-01
- – Chu, Tao
- – application/pdf
Randomness in Integrated Circuits with Applications in Device Identification and Random Number Generation
description- – RFID applications create a need for low-cost security and privacy in potentially hostile environments. To accomplish these goals of security and privacy, static identifiers and random numbers are required. Motivated by cost constraints, this thesis explores generating both identifiers and random numbers from existing CMOS circuitry, using a system of Fingerprint Extraction and Random Numbers in SRAM (FERNS). The identity results from the impact of manufacture-time physically random device threshold mismatch on the initial state of SRAM, and the randomness results from the impact of run-time physically random noise. FERNS is supported by an analytical model of the relative impacts of process variation and noise, and by experimental data from virtual tags, microcontroller memory, and the WISP UHF passive RFID tag. It is shown that virtual tags can be uniquely identified amongst a population of 160 using less than 50 bits of SRAM with an efficient matching algorithm. It is shown that a 128 bit true random number capable of passing statistical tests can be extracted from 256 bytes of SRAM. Based on these results and the observation that FERNS is well suited to passive applications, we conclude that FERNS is a viable approach to both identification and true random number generation in RFID tags.
- – 2007-01-01
- – application/pdf
Comprehensive Analysis of Leakage Current in Ultra Deep Sub-micron (UDSM) CMOS Circuits
description- – Aggressive scaling of CMOS circuits in recent times has lead to dramatic increase in leakage currents. Previously, sub-threshold leakage current was the only leakage current taken into account in power estimation. But now gate leakage and reverse biased junction band-to-band-tunneling leakage currents have also become significant. Together all the three types of leakages namely sub-threshold leakage, gate leakage and reverse bias junction band-to-band tunneling leakage currents contribute to more than 25% of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called loading effect and it leads to further increase in leakage current. On the other hand, sub-threshold leakage current decreases as more number of transistors is stacked in series. This is called stack effect. Previous works have been done that analyze each type of leakage current and its effect in detail but independent of each other. In this work, a pattern dependent steady state leakage estimation technique was developed that incorporates loading effect and accounts for all three major leakage components, namely the gate leakage, band to band tunneling leakage and sub-threshold leakage. It also considers transistor stack effect when estimating sub-threshold leakage. As a result, a coherent leakage current estimator tool was developed. The estimation technique was implemented on 65nm and 45nm CMOS circuits and was shown to attain a speed up of more than 10,000X compared to HSPICE. This work also extends the leakage current estimation technique in Field Programmable Gate Arrays (FPGAs). A different version of the leakage estimator tool was developed and incorporated into the Versatile Place&Route CAD tool to enable leakage estimation of design after placement and routing. Leakage current is highly dependent on the steady state terminal voltage of the transistor, which depends on the logic state of the CMOS circuit as determined by the input pattern. Consequently, there exists a pattern that will produce the highest leakage current. This work considers all leakage sources together and tries to find an input pattern(s) that will maximize the composite leakage current made up of all three components. This work also analyzes leakage power in presence of dynamic power in a unique way. Current method of estimating total power is to sum dynamic power which is ½?CLVDD2f and sub-threshold leakage power. The dynamic power in this case is probabilistic and pattern independent. On the other hand sub-threshold leakage is pattern dependent. This makes the current method very inaccurate for calculating total power. In this work, it is shown that leakage current can vary by more than 8% in time in presence of switching current.
- – 2007-01-01
- – application/pdf
Design and Development of TIMMI - An Interferometric Radar
description- – Interferometry has gained importance as a remote sensing technique to study topography, topographic change and volume and surface scattering properties of various natural targets. Interferometric radars rely on the ability to accurately measure amplitude and phase between signals received on two spatially separated antennas. The accuracy required for interferometric measurements place tight constraints on the performance of the radar hardware. This thesis details the development, construction and testing of a two-stage, two-channel Ku band downconverter ( also referred to as Dual Channel Downconverter or DDC)- which forms the core of the interferometer - to meet the requirements to make highly accurate interferometric measurements.
- – 2007-01-01
- – application/pdf
ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS
description- – ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOSAugust 2007BASAB DATTAB.S., G.G.S. INDRAPRASTHA UNIVERSITY, NEW DELHIM.S.E.C.E, UNIVERSITY OF MASSACHUSETTS AMHERSTDirected by: Professor Wayne P. BurlesonAggressive technology scaling and an increasing demand for high performance VLSI circuits has resulted in higher current densities in the interconnect lines and increasingly higher power dissipation in the substrate. Because a significant fraction of this power is converted to heat, an exponential rise in heat density is also experienced. Different activities and sleep modes of the functional blocks in high performance chips cause significant temperature gradients in the substrate and this can be expected to further increase in the GHz frequency regime. The above scenario motivates the need for a large number of lightweight, robust and power-efficient thermal sensors for accurate thermal mapping and thermal management. We propose the use of Differential Ring Oscillators (DRO) for thermal sensing at the substrate level, utilizing the temperature dependence of the oscillation frequency. They are widely used in current VLSI for frequency synthesis and on-die process characterization; hence provide scope of reusability in design. The DRO oscillation frequency decreases linearly with increase in temperature due to the decrease in current in the signal paths. In current starved inverter topology using the 45nm technology node, the DRO based thermal sensor has a resolution of 2°C and a low active power consumption of 25µW, which can be reduced further by 60-80% by power-gating the design. Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density as we move from substrate to higher metal levels. Thus, the deterioration of interconnect performance at extreme temperatures has the capability to offset the degradation in device performance when operating at higher than normal temperatures. We propose using lower-level metal interconnects to perform the thermal sensing. A resolution of ~5°C is achievable for both horizontal and vertical gradient estimation (using current generation time-digitizers). The time-digitization unit is an essential component needed to perform interconnect based thermal sensing in deep nanometer designs but it adds area and power overhead to the sensor design and limits the resolution of the wire-based sensor. We propose a novel sensor design that alleviates complexities associated with time-to-digital conversion in wire-based thermal sensing. The IBOTS or Interconnect Based Oscillator for Thermal Sensing makes use of wire-segments between individual stages of a ring-oscillator to perform thermal sensing using the oscillator frequency value as the mapping to corresponding wire temperature. The frequency output can be used to generate a digital code by interfacing the IBOTS with a digital counter. In 45nm technology, it is capable of providing a resolution of 1°C while consuming an active power of 250-360µW.
- – 2007-01-01
- – application/pdf
APPLICATIONS OF LDPC CODES FOR HYBRID WIRELESS OPTICAL AND MAGNETIC RECORDING SYSTEMS
description- – This thesis comprises of two parts. In the first, we improve the performance of existing hybrid FSO/RF communication systems. Conventional hybrid RF and optical wireless communication systems make use of independent and parallel Free Space Optical (FSO) and RF channels to achieve higher reliability than individual channels.This thesis is based on the idea that true hybridization can be accomplished only when both channels collaboratively compensate the shortcomings of each other and thereby, improve the performance of the system as a whole. We believe that optimization on the combined channel capacities instead of the individual channel capacities of the FSO and RF channels can increase the system availability by a large amount. Using analysis and simulation, we show that, by using Hybrid Channel Codes, wecan obtain more than two orders of magnitude improvement in bit error rates and many-fold increase in system availability over the currently existing best systems. Simulations also show that the average throughput obtained using the new system is over 35% better when compared to the present systems. The goodput is much higher because of the elimination of data repetition. Also by avoiding data duplication, we preserve to a great extent the crucial security benefits of FSO communications.The second half of the thesis deals with magnetic recording systems. Due to the insatiable and ever-increasing needs of data storage, novel techniques have to be developed to improve the capacity of magnetic recording channels. These capacity requirements translate to improving storage densities and using higher recording rates. For these channels, improvements even in the order of a tenths of a dB have a big impact on the storage densities of the recording device. Recently, LDPC codes have been constructed to achieve the independent and uniformly distributed (i.u.d.) capacity of partial response (PR) channels. The "guess algorithm" has been proposedfor memoryless channels, to improve the performance of iterative belief propagation decoding to that of Maximum Likelihood (ML) decoding. In the second part of this thesis, the "guess algorithm" is extended to channels with memory. It is shown using asymptotic density evolution analysis that the gains obtained using this algorithm onthese channels are more than those obtained over memoryless channels. The "guess algorithm" is further extended to magnetic recording channels which are characterized by ISI and additive white gaussian noise (AWGN). Simulations show that gains of upto one dB are possible on magnetic recording channels.
- – 2007-01-01
- – application/pdf
Current-sensed Interconnects: Static Power Reducation and Sensitivity to Temperature
description- – Global on-chip interconnects in deep sub-micron CMOS present challenges in satisfying delay constraints in the presence of noise and dramatic temperature variations, while minimizing energy consumption due to leakage and static power. Although repeaters are typically used to reduce delay and maintain signal integrity in long interconnects, they introduce significant area, power (both dynamic and leakage), delay, noise and design overhead as well as exacerbating variations due to their local power supply noise and temperature. Current-Sensing is an alternative to repeaters that transfers signals with no intermediate circuits by sensing current rather than voltage at the end of a long interconnect. Among the current sensing circuits, Differential Current-Sensing (DCS), which uses conventional CMOS inverters to drive differential signal, is preferred because of its high common-mode noise rejection. The DCS circuit is fast and simple in layout compared to repeater insertion despite significant static and leakage power which remains a barrier for broad application. Temperature variation throughout the chip also causes the timing uncertainty on interconnects to increase.This thesis addresses current-sensing interconnect circuit design in several aspects. First, it provides an improved differential current-sensing circuit called the differential leakage-aware sense amplifier (DLASA), that uses local power gating that results in 39.6% reduced leakage and static power compared to conventional differential current sensing. Secondly, thermal impact on interconnect is studied and temperature sensitivity is analyzed for interconnect circuits. Theoretical analysis is discussed as a base design guideline, then accurate simulation based experiments in 65nm, 45nm and 32nm CMOS technologies are used for verification from 25OC to 150OC. Thus this project provides a view of the year of technology toward 2013.
- – 2007-01-01
- – application/pdf
Logic Simulation Using Graphics Processors
description- – Logic Simulation is widely used to verify the logical correctness of hardware designs. In this work, we present the implementation of a generic graphics processor based logic simulator and compare it with the corresponding CPU (desktop) based implementation. The motivation for this study arises from the increasing computational power of graphics processors (GPUs). Graphics hardware performance is approximately doubling every six months, and they are out-pacing CPUs in raw computational power. GPUs are becoming increasingly programmable and their prices are falling steeply. Most desktops now come built-in with programmable graphics processors. The highly parallel nature of graphics computations enables GPUs to use additional transistors for computation, achieving higher arithmetic intensity with the same transistor count. Applications such as Ray Tracing, Fluid Modeling, Radiology imaging etc have shown speed-ups on graphics processors. This led us to investigate the use of GPUs to run concurrent algorithms for logic simulation. We present the implementation and analyze performance bottlenecks and finally draw conclusions as to whether the GPU can be used for speeding up the logic simulation algorithm.
- – 2007-01-01
- – application/pdf
Transfer Function and Impulse Response Synthesis using Classical Techniques
description- – This thesis project presents a MATLAB based application which is designed to synthesize any arbitrary stable transfer function. Our application is based on the Cauer synthesis procedure. It has an interactive front which allows inputs either in the form of residues and poles of a transfer function, in the form of coefficients of the numerator and denominator of the transfer impedance or in the form of samples of an impulse response. The program synthesizes either a single or double resistively terminated LC ladder network. Our application displays a chart showing the variation of stability of an impulse response with the addition of delay. An attempt is made to synthesize usually unstable impulse responses by calculating the delay that would make them stable.
- – 2007-01-01
- – application/pdf
POWER AMPLIFIER LINEARIZATION IMPLEMENTATION USING A FIELD PROGRAMMABLE GATE ARRAY
description- – The emphasis on higher data rates, spectral efficiency and cost reduction has driven the field towards linear modulation techniques such as quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), wideband code division multiple access (WCDMA), and orthogonal frequency division multiplexing (OFDM).The result is a complex signal with a non-constant envelope and a high peak-to-average power ratio. This characteristic makes these signals particularly sensitive to the intrinsic nonlinearity of the RF power amplifier (PA) in the transmitter. The nonlinearity will generate intermodulation (IMD) components, also referred to as out-of-band emissionor spectral re-growth, which interfere with adjacent channels. Such distortion, or so called Adjacent Channel Interference (ACI), is strictly limited by FCC and ETSI regulations. Meanwhile, the nonlinearity also causes in-band distortion which degrades the bit error rate performance. Typically, the required linearity can be achieved either by reducing power efficiency or by using linearization techniques. For a Class-A PA, simply "backing off" the input power level can improve linearity; however, for high peak to average power ration (PAPR) signals, this normallyreduces the power efficiency down to 10% while increasing heat dissipation up to 90%.When considering the vast number of base stations that wireless operators need toaccount for, increasing power consumption, or in other words, power back-off is not a viable tradeoff. Therefore, amplifier linearization has become an important technology and a desirable alternative to backing-off an amplifier in modern communications systems. In this work, a novel adaptive algorithm is presented for predistorter linearization of power amplifiers. This algorithm uses Pade-Chebyshev polynomials and a QR decomposition followed by back substitution to find the pre-distorter coefficients.This algorithm is implemented on a Field Programmable Gate Array (Stratix 1S80).The implementation provides improved linearization and also runs the algorithm fast enough so that the adaptive part can be done quickly. Yet another challenge was the integration of a transmitter, receiver and this adaptive algorithm into a single FPGA chip and its communication with a base station. The work thus presents a novel pre-distortion implementation technique using an FPGA and a soft processor (Nios 2) which provides significant intermodulation distortion suppression.
- – 2007-01-01
- – application/pdf
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